MOSFET Modeling with SPICE - Principles and Practice


In recent years, the international integrated circuit (IC) industry has enjoyed unprecedented growth. Interestingly, supply is now creating its own demand, as integrated circuits appear in a wider and more diverse set of applications. For a variety of reasons, Complementary Metal-Oxide-Semiconductor (CMOS) technology has emerged as the leading silicon choice, and clearly dominates the present marketplace.

This growth has spurred the continuing evolution of computer-aided design (CAD) technology for integrated circuit simulation. The SPICE circuit simulator long ago emerged as the de facto industry standard in this field, as is used today in several different forms. To simulate a CMOS integrated circuit, SPICE must make use of element models of the field-effect transistor (FET); these FET models provide a description of how a transistor will behave in the designed circuit. Thus, the FET models serve as the connection between the designed circuit and the underlying fabrication technology.

At this time, several trends are transforming FET model quality into a major issue. First, there has been rapid growth in low power CMOS technology; this imposes added requirements for model accuracy and robustness. Second, there has been a surge of interest in analog and mixed signal IC design; this design field places more stringent requirements on the finer details of FET modeling, and forces careful evaluation of topics which, in the past, could be safely neglected. Finally, a major trend is the emergence of the fabless design company; such a firm carries out integrated circuit design and then contracts the fabrication to a ``silicon foundry.'' In this business, circuit designers and their fabrication technology are separated both geographically and philosophically. Under these circumstances, the FET models serve as the critical ``communication vehicle'' between the circuit designer and the foundry.

It therefore behooves the circuit designer to become an ``educated model consumer'' of SPICE FET models. This text attempts to provide a ``single source'' reference book on the FET models used in ``mainstream'' versions of SPICE. A designer must work with the existing modeling ``infrastructure'', and make the best use of currently available simulation technology. This book carefully describes the FET models and various related issues. Chapter 1 introduces the basic reasons for the growth of the IC industry and the concomitant importance of SPICE simulation, while Chapter 2 describes the basic structure used to model FETs in SPICE. Chapter 3 reviews some basic concepts in semiconductor physics and small geometry effects in FETs; Chapter 4 compares these basic analytical results with more accurate numerical simulations, to illustrate the approximations used to derive the analytical expressions. Chapters 5 - 10 discuss the FET models currently in common use (Level 1, Level 2, Level 3, BSIM, HSPICE Level 28, and BSIM2), evaluating each model's strengths, weaknesses, behavior, and applicability for particular types of circuit design. It is carefully noted that the model equations represent an ``upper limit'' of what is possible from a particular type of model, while good parameter extraction is required to reach that limit. Chapters 11 and 12 address, respectively, two new models (BSIM3 and MOS Model 9) which are now being introduced. Chapter 13 discusses gate capacitance modeling and charge conservation, Chapter 14 discusses methods of modeling statistical process variations, and Chapter 15 considers methods of correlating the SPICE FET models and circuit-level results. Chapter 16 considers several ``candidate'' FET models, which may find use in SPICE in the near future; these models also serve to identify important trends in FET modeling. Chapter 17 briefly examines historical trends, the present situation, and future directions in analytical FET modeling.

The author hopes that this text will serve as a single reference source for circuit designers and model building engineers in this field. The discussion is intended to be complete and comprehensive, while providing a full set of bibliographic citations for detailed analysis.

This book was made possible by assistance from a number of individuals and organizations. I am particularly indebted to Paul Findley, Morgan Smith, Ali Rezvani, and their colleagues at VLSI Technology, Inc., San Jose, California, for providing the data which was used in the parameter extraction sections of this book, and to Hamed Emami, David Perejda, and their colleagues at Meta-Software, Inc., Campbell, California, for providing the copy of HSPICE which was used for all the parameter extraction and circuit simulation detailed in this text. I also wish to thank Prof. Gennady Gildenblat of Pennsylvania State University, University Park, Pennsylvania, Howard Russell of Opal Engineering, San Jose, California, and Jeff Deutsch of Deutsch Technology Research, Los Altos, California, for reading the manuscript and providing numerous helpful comments and suggestions. I also owe a debt to many colleagues with whom I continue to discuss FET modeling issues, including Peter Bendix, Christian Enz, Matthias Bucher, Jared Zerbe, John Cooley Jeff Deutsch, Mohammed Ismail, Richard Kaul, Ann Spratt, Alex Sinar, Steve Michael, and Robert Taft. Finally, I wish to thank Karen Gettman of Prentice-Hall for her patience as the editor for this project, and for seeing the effort through to its completion.

27 March 1996
Fletcher, Vermont