Analog Integrated Circuit Design and Modeling

Two Advanced Short Courses

Monterey, California, 9 - 14 December 1996
Lausanne, Switzerland, 16 - 21 February 1997


Purpose

Analog circuit design represents one of the most complex and sophisticated
tasks facing today's IC engineers. In these courses, leading practitioners
in the area will discuss the most important problems and their solutions on
an advanced level. In particular, the two courses will focus on basic and
advanced topics in the paper design and CAD of analog integrated circuits.
In the first course, the lecturers will discuss structures and design
techniques for state-of-the-art analog integrated circuit stages, such as
amplifiers, comparators, oscillators, PLLs, voltage converters and
references. The second course will provide up-to-the-minute information,
much of it previously unpublished, on the limitations of SPICE algorithms
and models (and how to overcome them), on advanced FET models such as
BSIM3 and the EKV model; the simulation of MOSFET matching; and the
difficult simulation problems associated with RF circuits, interconnects
and substrate noise.

Transistor-Level Design of Analog Integrated Circuits

This course will provide the latest techniques for the practical design of
the most important building blocks used in analog integrated circuits. The
topics to be discussed include the design of CMOS bias circuits and
op-amps; fast and high-accuracy sample-and-hold stages; comparators; AGC as
well as low-noise amplifiers; voltage-controlled oscillators and
phase-locked loops; on-chip switched-capacitor dc-dc voltage converters;
voltage references; and finally feedback frequency stabilization
techniques.

The course will be taught by leading industrial designers and university
researchers with many years of experience in the practical design of analog
ICs. It will provide state-of-the-art information on the most effective
methods currently available for analog integrated circuit design.

Modeling and Simulation of MOS Analog ICs

The aim of this course is to examine the limitations of the algorithms used
in SPICE, as well as the existing infrastructure for modeling FETs in
SPICE from the point of view of the circuit designer. To make the most
effective use of foundry MOS models, a circuit designer should be aware of
the strengths and weaknesses of SPICE algorithms, different model types,
and of how parameter extraction affects the final model quality.

The topics covered in the course will include the limitations of SPICE
algorithms and models, MOS modeling dedicated to low-voltage and
low-current circuit design, matching of MOS transistors, interconnect
modeling, behavioral modeling of analog mixed-signal circuits, and
simulation techniques for RF circuits and substrate noise coupling.

The speakers are leading experts in the area from high-technology companies
and universities.

Organization

These courses are part of an ongoing series of courses offered by MEAD
Microelectronics, Inc., an IC design company active in Switzerland and the
USA. The organization of these courses is performed with the help of a
Technical Committee consisting of R. Blauschild (Philips), M. Declercq, 
Ch. Enz (EPFL), Paul Gray (UC Berkeley), T. Hornak (HP Labs), Barrie 
Gilbert (ADI), W. Sansen (KUL), T. Schmerbeck (IBM), G. Temes (OSU), 
V. Valence (MEAD-EPFL), and E. Vittoz (CSEM).

For additional information contact:

MEAD Microelectronics Inc. 
7100 NW Grandview Drive 
Corvallis, Oregon 97330  (USA) 
telephone:  (541) 758-0828 
Fax:  (541) 752-1405
e-mail:  valence@mead.ch 

Course Location

Both courses will be held in beautiful Monterey, California. The lectures
will be given in the meeting rooms of the Doubletree Hotel in Monterey.
This hotel overlooks the scenic Monterey Bay; Fisherman's Wharf, Cannery
Row, the Monterey Bay Aquarium and Carmel-by-the-Sea are only minutes away.
The hotel offers a heated pool and spa; there are 15 championship golf
courses nearby. All rooms are newly appointed, and many offer spectacular
bay views. It is located at the Fisherman's Wharf, on the corner of Del
Monte Avenue and Pacific Street.

Hotel Reservations

A block of rooms has been reserved at the Doubletree Hotel, at a reduced
daily rate of $120 (single or double) for the participants of the course.
You must identify yourself as a course attendee when making your
reservation in order to receive the reduced rate.

Send your hotel reservations to the Doubletree Hotel, 2 Portola Plaza,
Monterey, CA 93940. Tel. (408) 649-4511; FAX (408) 649-4115.

Registrations MUST reach the hotel before November 6, 1996. After this
date, the reduced room rate (or even room availability) cannot be
guaranteed.

Fee Schedule

Fees include all lecture notes, three daily coffee breaks, and an evening
reception. The fee for one course is $1,000; for both courses taken by the
same person $1,750. A 10% discount applies for fully paid early
registrations received before November 6, 1996, as well as for university
faculty and students with IDs. The combined discounts cannot exceed 15%.

Company Purchase Orders are acceptable with the registration terms but all
fees must be fully paid before the course. NOBODY WILL BE ALLOWED TO
PARTICIPATE IN THE COURSE UNLESS THEIR FEES HAVE BEEN FULLY PAID.

All fees will be fully refunded if a cancellation is received by November
6, 1996. After this date, no refunds are possible, but the registration is
transferable to an alternate attendee, or can be used to pay for
participation in a future MEAD course. Unpaid registrants will be held
responsible for the fee unless they cancel by November 6, 1996. 

The number of places is limited, so register early!


Instructors

Narain Arora is Chief Scientist at Simplex Solutions, Inc. Prior to joining
Simplex, he was Consulting Engineer and Manager of the Device and Interconnect
Group at the Semiconductor Division of Digital Equipment Corp.  He has
published over 40 journal papers in the device and circuit characterization
and modeling area, and has authored a book "MOSFET Modeling for VLSI
Simulation: Theory and Practice", Springer-Verlag, NY, 1993.

Robert Blauschild, MSEE, UC Berkeley, 1973. He is Manager of Advanced
Development at Philips Semiconductor in Sunnyvale, CA. He has served for 14
years on the ISSCC program committee, has twice been a Guest Editor of the
Journal of Solid-State Circuits, and holds over a dozen patents in the
field of analog circuit design.

A. Paul Brokaw, BS, Oklahoma State University, spent his early years
investigating flashlight workings and disemboweling toasters. Later, he
worked at Well Surveys Inc., at Labko Scientific Inc., and at Arthur D.
Little Inc., as well as at Communication Technology Inc. In 1971, he moved
to Nova Devices, which became the Semiconductor Division of Analog Devices.
He is now an Analog Fellow. He has presented and published papers at
technical conferences and in IEEE journals, has been active in IEEE,
including several years on the ISSCC program committee, and is a Fellow of
the IEEE.

Christian C. Enz, PhD, Swiss Federal Inst. of Technology (EPFL), 1989.
Formerly co-founder and director of Smart Silicon Systems, an IC design
company, where he designed low-power and low-noise CMOS ICs. In 1992 he
joined the Electronics Laboratory of the EPFL where he is currently an
Assistant Professor. His technical interests are in device modeling and
low-power analog CMOS circuit design. He authored or co-authored more than
40 scientific papers and has contributed to numerous conference
presentations and advanced engineering courses.

Daniel Foty is the President of Gilgamesh Associates, a consulting and
research firm specializing in MOS model construction, implementation, and
usage. He is the author of "MOSFET Modeling with SPICE - Principles and
Practice", which was recently published by Prentice-Hall.

Michael Green, PhD, UCLA, 1991. Since 1991 he has been a faculty member of
the Department of Electrical Engineering at the University at Stony Brook,
NY, where he is currently an Associate Professor. He was an IC design
engineer at National Semiconductor Corp. from 1984 to 1987. His research
interests include analog IC design, circuit simulation and the theory of
nonlinear circuits. He has received the IEEE Guillemin-Cauer Award and the
IEEE Baker Award. He is currently the recipient of a National Young
Investigator Award from the National Science Foundation.

Kenneth Martin, PhD, Univ. of Toronto, 1980. He worked at Bell-Northern
Research, where he did some of the early fundamental work on SC networks;
from 1980 to 1991, he was a professor at UCLA. He is currently the Stanley
Ho Professor of Microelectronics at the University of Toronto. He was a
consultant to many companies on CMOS, BiCMOS and GaAs ICs and on DSP
algorithms. He won the IEEE Outstanding Young Engineer award and ISSCC
Beatrice Winner Best Paper Award. He is a Fellow of the IEEE.

Marcel Pelgrom, PhD, Twente Univ. of Technology, 1988. In 1979 he joined
Philips Research Laboratories, Eindhoven, the Netherlands, where he
designed digital CCD memories and analog CCD delay lines, and investigated
the matching behavior of MOS devices, digital picture correlators, audio
D/A conversion and various analog circuits. From 1989 to 1996 he was a
team leader for high-speed A/D conversion and related subjects. Since 1996,
Dr. Pelgrom has headed the Analog Integrated Electronics group of Philips
Research Labs.

Behzad Razavi, PhDEE, Stanford University, 1991. He was with AT&T Bell
Labs, Holmdel, NJ, and HP Labs, Palo Alto, CA, and recently joined UCLA as
an associate professor. He is a member of the ISSCC Technical Program
Committee, an Associate Editor of JSSC, and recipient of several awards at
ISSCC and ESSCIRC. He has published two books with IEEE Press.

Gabor C. Temes, PhD, Univ. of Ottawa, 1961. Professor, Electrical and
Computer Engineering Dept., Oregon State Univ., Prof. Emeritus, UCLA.
Formerly with UCLA, Ampex Corp., Stanford Univ. and BNR. Fellow, IEEE.
Received the Technical Achievement Award and the Education Award of the
IEEE CAS Society as well as the IEEE Centennial Medal. He wrote many books
and papers on discrete and integrated circuit design.

Nishath Verghese, Ph.D., Carnegie Mellon University, 1995.  Senior Member
of Technical Staff at Cadence Design Systems, San Jose, CA where he is the
principal developer of verification tools for substrate/noise coupling in
analog and mixed-signal ICs.  Dr. Verghese has several publications in the
areas of parasitic crosstalk analysis, layout verification and synthesis.
He is co-author of the book "Simulation Techniques and Solutions for 
Mixed-Signal Coupling in Integrated Circuits," Kluwer, 1995. He has prior
analog/mixed-signal IC design experience having designed several A/D 
converters both in graduate school and at Texas Instruments, Dallas.


Course 1: Transistor-Level Design of Analog ICs

Monday - December 9

8:30-10:00 am
Review of Basic Current Mirrors and Single-Stage Amplifiers
Ken Martin, University of Toronto
Simple CMOS current mirror, common-source amplifier, source follower,
common-gate amplifier, source-degenerated current mirrors,
high-output-impedance current mirrors, cascode gain stage, MOS differential
pair and gain stage, bipolar current mirror, bipolar gain stage, frequency
response.

10:30-12:00 am and 1:30-3:00 pm
CMOS Amplifiers
Ken Martin, University of Toronto
Two-stage op-amp, feedback and op-amp compensation, supply-insensitive
biasing, wide-swing current mirrors, enhanced-output-impedance mirrors,
folded-cascode op-amp, current mirror op-amp, fully-differential op-amps,
common-mode feedback circuits, current-feedback op-amps.

3:30-5:00 pm
Comparators and Sample-and-Hold Amplifiers
Behzad Razavi, UCLA
Analysis and design of comparators and SHAs in CMOS, bipolar, and BiCMOS
technologies; fundamental issues in supply and power scaling; performance
metrics and figures of merit; comparator topologies; high-speed
comparators; offset cancellation techniques; SHA architectures; dynamic
range-power-speed trade-offs; low-voltage high-speed SHA design; case
studies.
(Continued on Tuesday morning)

Tuesday - December 10

8:30-10:00 am
Comparators and Sample-and-Hold Amplifiers
Behzad Razavi, UCLA
(Continued from Monday afternoon session)

10:30-12:00 am
Low-Noise and AGC Amplifiers
Robert Blauschild, Philips Semiconductors
Low-noise amplification of fiberoptic, RF, and magnetically-coupled signals
using MOS, bipolar, and BiCMOS technologies. Automatic gain-control circuits
with emphasis on linearity, noise, and bandwidth considerations.
Low-voltage topologies. Practical limitations imposed by substrate,
package, and board parasitics.

1:30-3:00 pm
Voltage-Controlled Oscillators
Behzad Razavi, UCLA
Basic concepts and models; oscillator topologies; design issues in CMOS and
bipolar ring, relaxation, and LC oscillators; frequency control techniques;
jitter and phase noise; power-speed-noise trade-offs; high-speed design
examples.

3:30-5:00 pm
Phase-Locked Loops
Robert Blauschild, Philips Semiconductors
Phase/Frequency detector, VCO, loop filter, and limiter topologies.
Advantages and disadvantages of alternatives based on application
requirements. Rejection/minimization of noise due to basic circuit design
and parasitics. Implementations for low-voltage and high-speed operation.
Compatible logic families for mixed-signal applications such as
clock recovery and synthesizers.

Wednesday - December 11

8:30-10:00 am
Switched-Capacitor Supply Voltage Down- and Up-Converters
Gabor Temes, Oregon State University
Charge-switching voltage dividers, multipliers and inverters. Applications
in battery-operated equipment (watches, implanted medical devices). Bias
and clock-signal voltage up-converters, and their use in low-voltage
sampled-data circuits. The analysis and design of SC voltage converters.

10:30-12:00 am
Zener/Avalanche Diode Reference Circuit Design
Paul Brokaw, Analog Devices
Typical Zener/avalanche diode characteristics. The advantages of buried
construction contrasted with surface breakdowns. Temperature sensitivity of
the breakdown voltage and compensation methods. Excitation, voltage scaling
and buffering circuits. Techniques for trimming both the output voltage and
temperature behavior. Fundamental Zener noise behavior. The impact of
various circuit techniques on overall noise.

1:30-3:00 pm
Bipolar Transistor Voltage Reference Circuit Design (and What the Band Gap
Has To Do With It)
Paul Brokaw, Analog Devices
The band gap voltage reference principle as used in some practical circuit
design techniques. The fundamental noise sources common to transistor
references and means to maximize the reference voltage-to-noise ratio.
Layout design issues and techniques for starting, temperature
stabilization, curvature correction, and voltage/temperature trimming.

3:30-5:00 pm
Feedback and Frequency Stabilization Techniques
Paul Brokaw, Analog Devices
Closed-loop performance and stability; circuit techniques for stabilizing
closed loops. An intuitive explanation of some common analytical results:
the whys and hows of "pole splitting" frequency compensation. The
right-half-plane zero effect in frequency-compensated inverter stages; 
a technique for evaluating its importance in a given circuit; methods 
for reducing its effect. Some handy techniques and rules of thumb for 
using Bode Plot analysis. Absolutely and conditionally stable 
characteristics, and the difference between them.


Course 2: Modeling and Simulation of MOS Analog ICs

Thursday - December 12

8:30-10:00 am
An Overview of the SPICE FET Modeling Infrastructure
Daniel Foty, Gilgamesh Associates
A detailed review of the modeling of FET devices in SPICE. The evolution of
FET models, from the original Level 1 model up through the most recent
developments, such as BSIM3; sample results. Related issues, such as gate
capacitance modeling, systematic process variations, and correlation with
circuit results. Future trends in MOS modeling.

10:30-12:00 am
Benchmarking FET Models for Circuit Design
Daniel Foty, Gilgamesh Associates
The behavior of several popular MOS models. Proactive tests which can be
carried out on foundry MOS models before their use in circuit design.
Methods for determining whether the model shortcomings are caused by
structural deficiencies in the model formulation or by poor parameter
extraction procedures. The difference between digital and analog design
requirements.

1:30-5:00 pm
SPICE: Its Use, Its Limitations and How to Overcome Them
Michael Green, SUNY
The numerical algorithms on which SPICE is based. The interaction of these
algorithms with certain key fundamental aspects of circuits - e.g., circuit
topology and device modeling. In-depth discussion of the following topics:
dc operating point analysis issues, including convergence and stability;
modeling; distortion analysis; transient analysis issues, including
time-step errors and simulation near metastable states; issues regarding
the simulation of RF circuits; alternatives to SPICE.

Friday - December 13

8:30-12:00 am
MOS Modeling Dedicated to Low-Voltage and Low-Current Circuit Design
Christian Enz, EPFL
The basic long-channel static model revisited: pinch-off voltage, modes of
operation, current and transconductance in weak, moderate and strong
inversion. Second-order effects: channel-length modulation, mobility
reduction, velocity saturation, short- and narrow-channel effects,
non-uniform doping. Quasi-static model: charges in weak and strong
inversion. First-order non-quasi-static model. Noise model: thermal noise
in weak and strong inversion, flicker (1/f) noise. Temperature effects. The
EKV model: from hand calculation to computer simulation, pinch-off vs. gate
voltage measurement, parameter extraction, experimental results.

1:30-5:00 pm
Matching of MOS Transistors
Marcel Pelgrom, Philips Research Labs
Basic discussion of the factors affecting the matching properties of MOS
transistors. The two key aspects: deterministic offsets and random offset.
Random offset in the threshold voltage, in the current factor and in the
substrate coefficient. The development over process generations and a
comparison of different processes. The use of practical matching data in
circuit design as illustrated by some examples.

Saturday - December 14

8:30-12:00 am
Interconnect Modeling
Narain Arora, Simplex Solutions, Inc.
An overview of interconnect issues in chip design; interconnect scaling
laws, interconnect as a parasitic element, numerical and analytical methods
of calculating lumped R, C and L of the interconnects. The verification and
calibration of interconnect capacitance models; RC models for full chip
extraction; the impact of process variations on the propagation delay due
to interconnects.

1:30-5:00 pm
Simulation of Substrate/Noise Coupling in Analog and Mixed-Signal ICs
Nishath Verghese, Cadence Design Systems
Overview of the various sources of noise and methods of coupling in ICs
with emphasis on systematic noise coupling mechanisms from switching
voltage and current through the substrate, interconnects and package.
Discussion of substrate coupling and techniques for its analysis.
Modeling the substrate using simple R(C) models. Modeling chip/package
power distribution. Higher-level simulation and modeling of switching
noise in large mixed-signal designs. Application of the modeling/simu-
lation techniques to design and verification of industrial ICs.


-------------------------------------------------

Course 1: Transistor-Level Design of Analog ICs

This course will provide the latest techniques for the practical design of
the most important building blocks used in analog integrated circuits. The
topics to be discussed include the design of CMOS bias circuits and
op-amps; fast and high-accuracy sample-and-hold stages; comparators; AGC as
well as low-noise amplifiers; voltage-controlled oscillators and
phase-locked loops; on-chip switched-capacitor dc-dc voltage converters;
voltage references; and finally feedback and frequency stabilization
techniques.

The course will be taught by leading industrial designers and university
researchers with many years of experience in the practical design of analog
ICs. It will provide state-of-the-art information on the most effective
methods currently available for analog integrated circuit design.

Ken Martin, University of Toronto
Review of Basic Current Mirrors and Single-Stage Amplifiers
CMOS Amplifiers

Behzad Razavi, UCLA
Comparators and Sample-and-Hold Amplifiers
Voltage-Controlled Oscillators

Robert Blauschild, Philips Semiconductors
Low-Noise and AGC Amplifiers
Phase-Locked-Loops

Gabor Temes, Oregon State University
Switched-Capacitor Supply Voltage Down- and Up-Converters

Paul Brokaw, Analog Devices
Zener/Avalanche Diode Reference Circuit Design
Bipolar Transistor Voltage Reference Circuit Design
Feedback and Frequency Stabilization Techniques


Course 2: Modeling and Simulation of MOS Analog ICs

The aim of this course is to examine the limitations of the algorithms used
in SPICE, as well as the existing infrastructure for modeling FETs in
SPICE from the point of view of the circuit designer. To make the most
effective use of foundry MOS models, a circuit designer should be aware of
the strengths and weaknesses of SPICE algorithms, different model types,
and of how parameter extraction affects the final model quality.

The topics covered in the course will include the limitations of SPICE
algorithms and models, MOS modeling dedicated to low-voltage and
low-current circuit design, matching of MOS transistors, interconnect
modeling, behavioral modeling of analog mixed-signal circuits and
simulation techniques for RF circuits and substrate noise coupling.

The speakers are leading experts in the area from high-technology companies
and universities.

Daniel Foty, Gilgamesh Associates
An Overview of the SPICE FET Modeling Infrastructure
Benchmarking FET Models for Circuit Design

Michael Green, SUNY
SPICE: Its Use, Its Limitations and How to Overcome Them

Christian Enz, EPFL
MOS Modeling Dedicated to Low-Voltage/Low-Current Circuit Design

Marcel Pelgrom, Philips Research Labs
Matching of MOS Transistors

Narain Arora, Simplex Solutions, Inc.
Interconnect Modeling

Nishath Verghese, Cadence Design Systems
Simulation of Substrate/Noise Coupling in Analog and Mixed Signal ICs