The SPICE FET Models: Pitfalls and Prospects
(Are you an educated model consumer?)
The 33rd Design Automation Conference
Las Vegas, Nevada (USA)
5 June 1996
8:30 - 10 am
(Click here for information on downloading the class slides.)
(Click here to view the extended abstract.)
(Click here to view the DAC program booklet description.)
On June 5th, 1996, Daniel Foty, the President of Gilgamesh Associates,
presented "The SPICE FET Models: Pitfalls and Prospects" at the 33rd Design
Automation Conference (DAC), in Las Vegas, Nevada.
This class was targetted at the circuit design user of SPICE FET models, and was
intended to improve the level of understanding of the FET models employed in
SPICE, along with raising the effectiveness of CMOS circuit design. Attendees
were treated to a practical discussion of the various issues that arise
in analytical FET models, potential circuit design pitfalls due to inherent
model shortcomings, and the suitability of models for various types of circuit
design (e.g., digital design vs. analog design).
Topics which were covered included:
Comments on the tutorial and suggestions for future tutorials are welcome, and
should be sent Daniel Foty at
- The growth of CMOS technology and the emergence of the fabless design industry.
- The formal structure of analytical FET modeling in SPICE.
- An examination of the evolution of the FET models presently in widespread use.
This will include a discussion of model strengths, weaknesses, applicability,
and circuit simulation usage.
- Modeling the active gate capacitance.
- Methods of accounting for process variations.
- Correlating models and hardware.
- Emerging new FET model candidates.
- A discussion of the future of analytical FET modeling for use in circuit
simulation. This topic is particularly important at this time, as new models
are being included in the SPICE circuit simulator. However, the increasingly
empirical character of these models is causing serious problems for the
practicing circuit designer.