Course 1: Transistor-Level Design of Analog ICs
Monday - December 9
8:30-10:00 am
Review of Basic Current Mirrors and Single-Stage Amplifiers
Ken Martin, University of Toronto
Simple CMOS current mirror, common-source amplifier, source follower,
common-gate amplifier, source-degenerated current mirrors,
high-output-impedance current mirrors, cascode gain stage, MOS differential
pair and gain stage, bipolar current mirror, bipolar gain stage, frequency
response.
10:30-12:00 am and 1:30-3:00 pm
CMOS Amplifiers
Ken Martin, University of Toronto
Two-stage op-amp, feedback and op-amp compensation, supply-insensitive
biasing, wide-swing current mirrors, enhanced-output-impedance mirrors,
folded-cascode op-amp, current mirror op-amp, fully-differential op-amps,
common-mode feedback circuits, current-feedback op-amps.
3:30-5:00 pm
Comparators and Sample-and-Hold Amplifiers
Behzad Razavi, UCLA
Analysis and design of comparators and SHAs in CMOS, bipolar, and BiCMOS
technologies; fundamental issues in supply and power scaling; performance
metrics and figures of merit; comparator topologies; high-speed
comparators; offset cancellation techniques; SHA architectures; dynamic
range-power-speed trade-offs; low-voltage high-speed SHA design; case
studies.
(Continued on Tuesday morning)
Tuesday - December 10
8:30-10:00 am
Comparators and Sample-and-Hold Amplifiers
Behzad Razavi, UCLA
(Continued from Monday afternoon session)
10:30-12:00 am
Low-Noise and AGC Amplifiers
Robert Blauschild, Philips Semiconductors
Low-noise amplification of fiberoptic, RF, and magnetically-coupled signals
using MOS, bipolar, and BiCMOS technologies. Automatic gain-control circuits
with emphasis on linearity, noise, and bandwidth considerations.
Low-voltage topologies. Practical limitations imposed by substrate,
package, and board parasitics.
1:30-3:00 pm
Voltage-Controlled Oscillators
Behzad Razavi, UCLA
Basic concepts and models; oscillator topologies; design issues in CMOS and
bipolar ring, relaxation, and LC oscillators; frequency control techniques;
jitter and phase noise; power-speed-noise trade-offs; high-speed design
examples.
3:30-5:00 pm
Phase-Locked Loops
Robert Blauschild, Philips Semiconductors
Phase/Frequency detector, VCO, loop filter, and limiter topologies.
Advantages and disadvantages of alternatives based on application
requirements. Rejection/minimization of noise due to basic circuit design
and parasitics. Implementations for low-voltage and high-speed operation.
Compatible logic families for mixed-signal applications such as
clock recovery and synthesizers.
Wednesday - December 11
8:30-10:00 am
Switched-Capacitor Supply Voltage Down- and Up-Converters
Gabor Temes, Oregon State University
Charge-switching voltage dividers, multipliers and inverters. Applications
in battery-operated equipment (watches, implanted medical devices). Bias
and clock-signal voltage up-converters, and their use in low-voltage
sampled-data circuits. The analysis and design of SC voltage converters.
10:30-12:00 am
Zener/Avalanche Diode Reference Circuit Design
Paul Brokaw, Analog Devices
Typical Zener/avalanche diode characteristics. The advantages of buried
construction contrasted with surface breakdowns. Temperature sensitivity of
the breakdown voltage and compensation methods. Excitation, voltage scaling
and buffering circuits. Techniques for trimming both the output voltage and
temperature behavior. Fundamental Zener noise behavior. The impact of
various circuit techniques on overall noise.
1:30-3:00 pm
Bipolar Transistor Voltage Reference Circuit Design (and What the Band Gap
Has To Do With It)
Paul Brokaw, Analog Devices
The band gap voltage reference principle as used in some practical circuit
design techniques. The fundamental noise sources common to transistor
references and means to maximize the reference voltage-to-noise ratio.
Layout design issues and techniques for starting, temperature
stabilization, curvature correction, and voltage/temperature trimming.
3:30-5:00 pm
Feedback and Frequency Stabilization Techniques
Paul Brokaw, Analog Devices
Closed-loop performance and stability; circuit techniques for stabilizing
closed loops. An intuitive explanation of some common analytical results:
the whys and hows of "pole splitting" frequency compensation. The
right-half-plane zero effect in frequency-compensated inverter stages;
a technique for evaluating its importance in a given circuit; methods
for reducing its effect. Some handy techniques and rules of thumb for
using Bode Plot analysis. Absolutely and conditionally stable
characteristics, and the difference between them.